1. Field of the Invention
The present invention relates generally to the field of information processing, and more particularly, to increasing the processing speed of a data driven information processor.
2. Description of the Related Art
A data driven processor which is based on the data driven principles is supposed to be an inherently natural information processing method and a generic term for a series of processors developed from research projects to effectively execute an object program directly converted from an executable high-level language.
The data driven principles will be described below. Instructions of a program attain an executable state if argument data necessary for its execution all arrives in the form of token (firing). An instruction upon thus becoming executable is sent to a function processor together with its parameter data and an address for an execution result. The processing of determining if the instruction is executable or not and the processing of sending an executable instruction to the function processor together with its parameter data and the address for execution result are implemented by a firing control unit.
A corresponding instruction is executed in the function processor and the result of execution of the instruction is transferred in the form of token as argument data for an instruction to be executed next based on the address.
Since execution of an instruction is driven in response to the arrival of a token, such computing method is called data driven method. FIG. 1 is a diagram for use in illustration of the data driven principles. An instruction fires in response to the arrival of a token from the right or left input arc. The data of operation result (the result of executing the instruction) is then output as a token to the output arc.
The principles are described in IWANAMIJOUHOUKAGAKUJITEN, Iwanami, pp. 494-497, 1990.
The data driven information processor is a system including a cyclic pipeline connection of a data pair producing unit for firing control (hereinafter alternatively referred to as firing control unit), a function processing unit (hereinafter alternatively referred to as FP), a program storing unit (hereinafter alternatively referred to as PS), and a data input/output control portion (hereinafter alternatively referred to as I/O).
FIG. 2 is a block diagram showing the structure of essential portions of such a data driven processor. Referring to FIG. 2, a processor including a cyclic pipeline connection of basic functions such as a firing control (matching) unit, a function processing unit, a program storing unit, a data input/output control portion will be described by way of illustration.
This system employs as a basic configuration for data transfer and processing, a cascade connection of temporary storing units (data latches) based on hand shaking type data transfer control using a plurality of C elements (self-timed transfer control elements) as shown in FIG. 3. A data packet which is a working packet of a physical standard autonomously selects a flow path within the configuration by a self path selecting function, and therefore, as it is sequentially processed by the functional elements for passage therethrough, execution of information processing also autonomously proceeds. Introducing such system removes a system bus, a system clock, a centralized processor and the like from processors, and control of the entire system is completely distributed.
The processing speed of the data driven processor is essentially determined based on the internal circuit configuration of the C elements in FIG. 3 and the natural scientific properties of the device. Determining the internal circuit configuration of the C elements therefore determines possible processing time for inter-stage processing between cascade connection networks of temporary storing units according to the hand shaking type data transfer control under these conditions.
In a usual operation, the operation is divided into lower-order operation elements, which are processed on a several-stage-basis, in other words pipeline dividing processing is conducted.
FIG. 4 is a diagram partially showing the configuration of a conventional data driven information processor. Data driven information processor 1C includes a series-connection of processing portions 3A, 3B, and 3C. A data packet input to the processor is processed by processing portion 3A and output to processing portion 3B. Processing portion 3B receives the data packet output from processing portion 3A and processes and outputs the packet to processing portion 3C. Processing portion 3C receives the data packet output from processing portion 3B processes the data packet for output.
Among the data driven information processing elements, there is a processing portion which requires processing time relatively longer than the other processing portions, which makes difficult pipeline dividing processing or there is a case in which the pipeline dividing processing is inherently difficult.
The pipeline dividing processing is difficult when mismatches arise with respect to standard processing time by the other processing portions if such pipeline dividing processing is conducted in the case of multiplication processing, for example, in other words the processing time is extremely short or long. The pipeline dividing processing is inherently difficult, for example, in the case of the main processing of the firing control portion.
FIG. 5 is a diagram showing an example of a logic circuit for a processing portion which requires processing time relatively longer than the other processing portions, and corresponds to the internal configuration of processing portion 3B is FIG. 4.
Processing in the example shown in FIG. 5 proceeds as follows. The processing portion receives a data packet. Stated differently, the signal on a C1 terminal 971 is pulled to an H level with the signal on an RO terminal 973 being at an L level, while a necessary L level or H level is applied to a D terminal 977 as information. After a certain time period determined by the internal circuit configuration of the C elements, an H level pulse is output from the CP terminal of C element 901 to the CK terminal of a data latch 921, and necessary data is temporarily held in data latch 921. Then, if the RO terminal of C element 911 with delay in the next stage is at an H level (which level indicates that no packet is present in the stage), in other words if the R1 terminal of C element 901 is at an H level, an L level is output from the CO terminal of C element 901 to the C1 terminal of C element 911 with delay. Accordingly, after a certain time period as is the case with C element 901, an H level pulse is output from the CP terminal of C element 911 with delay to the CK terminal of a data latch 922, and the data is temporarily held in data latch 922 (the packet is transferred). A processing portion 931 takes in necessary information from the Q terminal of data latch 922 for executing processing, and outputs the result of execution to a data latch 923. Based on the processing time by processing portion 931, in other words in response to completion of output of the result of execution to data latch 923 by processing portion 931 (time delay by C element 911 with delay is set to cause the above-described operation), an L level and an H level are output from the CO terminal and RO terminal of C element 911 with delay, respectively.
More specifically, this stage does not accept a packet from a preceding stage for a longer period of time as compared to the other stages, based on the processing time by processing portion 931. Thereafter, the packet is transferred in the same order as a transfer of signal at the time of packet transfer from the stage of C element 901 to the stage of C element 911 with delay.